The output of a digital Hall effect sensor is NPN (current sinking, open
collector), as shown in Figure 4-1. The illustration shows the outputs
in the actuated (ON) state.
Current sinking derives its name from the fact that it “sinks current from a
load.” The current flows from the load into the sensor. Current sinking
devices contain NPN integrated circuit chips. The physics of chip
architecture and doping are beyond the scope of this book.
Like a mechanical switch, the digital sensor allows current to flow when
turned ON, and blocks current flow when turned OFF. Unlike an ideal
switch, a solid state sensor has a voltage drop when turned ON, and a
small current (leakage) when turned OFF. The sensor will only
switch low level DC voltage (30 VDC max.) at currents of
20 mA or less. In some applications, an output interface may
be current sinking output, NPN.
Figure 4-2 represents an NPN (current sinking) sensor. In
this circuit configuration, the load is generally connected
between the supply voltage and the output terminal
(collector) of the sensor. When the sensor is actuated, turned
ON by a magnetic field, current flows through the load into
the output transistor to ground. The sensor’s supply voltage
(VS) need not be the same value as the load supply (VLS);
however, it is usually convenient to use a single supply. The
sensor’s output voltage is measured between the output terminal
(collector) and ground (-). When the sensor is not
actuated, current will not flow through the output transistor
(except for the small leakage current). The output voltage, in this
condition, will be equal to VLS (neglecting the leakage
current). When the sensor is actuated, the output voltage will drop
to ground potential if the saturation voltage of the output
transistor is neglected. In terms of the output voltage, an NPN
sensor in the OFF condition is considered to be normally
high.
Source pdf
http://www.honeywell-sensor.com.cn/prodinfo/
magnetic_position/technical/chapter4.pdf
ELECTRICAL INTERFACE FOR DIGITAL HALL DEVICES
The output stage of a digital Hall switch is simply an open-collector
npn transistor. The rules for use are the same as those for any similar
switching transistor.
When the transistor is OFF, there is a small output leakage current
(typically a few nanoamperes) that usually can be ignored, and a
maximum (breakdown) output voltage (usually 24 V), which must not
be exceeded.
When the transistor is ON, the output is shorted to the circuit
common. The current flowing through the switch must be externally
limited to less than a maximum value (usually 20 mA) to prevent
damage. The voltage drop across the switch (VCE(sat)) will increase for
higher values of output current. You must make certain this voltage is
compatible with the OFF, or “logic zero,” voltage of the circuit you wish
to control.
Hall devices switch very rapidly, with typical rise and fall times in
the 400 ns range. This is rarely significant, because switching times
are almost universally controlled by much slower mechanical parts.
COMMON INTERFACE CIRCUITS
Figure 17 illustrates a simplified schematic symbol for Hall digital
switches. It will make further explanation easier to follow.
Interface for digital logic integrated circuits usually requires only an
appropriate power supply and pull-up resistor.
With current-sinking logic families, such as DTL or the popular
7400 TTL series (figure 18A), the Hall switch has only to sink one unitload
of current to the circuit common when it turns ON (1.6 mA maximum
for TTL). In the case of CMOS gates (figure 18B), with the
exception of switching transients, the only current that flows is through
the pull-up resistor (about 0.2 mA in this case).
Loads that require sinking currents up to 20 mA can be drivendirectly
by the Hall switch
A good example is a light-emitting diode (LED) indicator that
requires only a resistor to limit current to an appropriate value. If the
LED drops 1.4 V at a current of 20 mA, the resistor required for use
with a 12 V power supply can be calculated as:
The nearest standard value is 560 , resulting in the circuit of
figure 19.
Source pdf
http://www.allegromicro.com/en/Products/Design/an/an27701.pdf
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